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International Journal of Engineering and Advanced Research Technology

Volume 4 Issue 5 (May 2018)

S.No. Title & Authors Page No View
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Title : High speed and low power Hybrid carry skip adder using DMFA

Authors : Santhosh N.S, Shivarudraiah M.R, Amaresha S.K

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Abstract :

The Adders are the integral part of the arithmetic and logic unit, hence increasing the performance of an adder is very important [1]. The Hybrid carry skip adder has better speed and less power utilization compare to conventional adders. In the modified carry skip adder, higher speed is achieved by concatenation and incrimination techniques. In addition, multiplexer in the skip logic of Conventional CSKA are replaced by use of AND-OR-Invert and OR-AND-Invert logic [3]. Then Hybrid CSKA using dual mode full adder (DMFA) is designed, which will replace the chain of ripple carry adders (RCA) present in the Hybrid carry skip adder with DMFA and Parallel prefix networks such as Brent-kung is  used as a middle of the stage to achieve higher speed. The Proposed hybrid CSKA structure is analyzed by comparing the parameters of power, speed and area with a conventional carry skip adder and modified carry skip adder using 180 nm CMOS technology. Finally, ASIC implementation of Hybrid carry skip adder using DMFA is carried out by cadence Encounter tool and it start from pad creation, floor planning, power planning, placement and routing  of designed Standard cell.

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Title : Functional Verification of AHB Bus Matrix with UVM Methodology

Authors : Praveena H U, Santhosh N S, Amaresha S K

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Abstract :

The AHB Bus matrix is enables the parallel access to shared slaves by multiple masters. The routing of the transfers from masters to the slaves is based on the arbitration scheme. Bus matrix enables the multiple AHB masters to connect to the multiple AHB slaves. Bus matrix will decode the transfer control signals, routes the transfer from master to the corresponding slave and response back from slave to the master with valid ready handshake which obey the AMBA AHB protocol specification. The design is verified with verification environment developed with the UVM methodology, which enables the more flexibility and greater control with the reusability.

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